Semiconductor device with reduced via resistance
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United States of America Patent
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Apr 24, 2018
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app pub date -
Mar 23, 2016
filing date -
Jul 24, 2014
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Abstract
A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.
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