Differential odd integer divider
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United States of America Patent
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Apr 17, 2018
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app pub date -
Nov 14, 2014
filing date -
Nov 14, 2014
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Abstract
A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.
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