Dummy gate placement methodology to enhance integrated circuit performance

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United States of America Patent

PATENT NO 9947765
SERIAL NO

15351657

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Abstract

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A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

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TEXAS INSTRUMENTS INCORPORATEDDALLAS TX

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baldwin, Gregory Charles Plano, US 11 98
Choi, Younsung Allen, US 19 33
Ekbote, Shashank Allen, US 19 325

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