Waveguide formation using CMOS fabrication techniques

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United States of America Patent

PATENT NO 9946022
SERIAL NO

15365548

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Abstract

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Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

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Patent Owner(s)

Patent OwnerAddress
MASSACHUSETTS INSTITUTE OF TECHNOLOGY77 MASSACHUSETTS AVENUE CAMBRIDGE MA 02139

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Atabaki, Amir Hossein Medford, US 4 77
Mehta, Karan Kartik Cambridge, US 4 77
Orcutt, Jason Scott Katonah, US 15 265
Ram, Rajeev Jagga Arlington, US 21 169

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