Digital-to-analog converter with improved linearity
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United States of America Patent
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Apr 10, 2018
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app pub date -
Aug 31, 2017
filing date -
Aug 31, 2017
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Abstract
A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.
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