Memory system and control method of memory system

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United States of America Patent

PATENT NO 9940274
APP PUB NO 20170046286A1
SERIAL NO

15064930

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Abstract

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According to one embodiment, an interface of a memory system includes a circuit configured to adjust output resistance for data output. When the circuit has received a command in a second state, the circuit adjusts output resistance during a first period. The first period is a period from when the interface completes reception of the command to when the interface starts transmission of data read from the memory. The second state is a state in which power consumption is lower than that in a first state in which operation is caused by a command.

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Patent Owner(s)

Patent OwnerAddress
KIOXIA CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kurakata, Shigeo Fujisawa, JP 18 150
Nakata, Daisuke Kamakura, JP 85 715
Nakata, Masashi Yokohama, JP 124 928

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