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United States of America Patent

PATENT NO 9934862
SERIAL NO

15424065

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Abstract

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Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

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Patent Owner(s)

Patent OwnerAddress
EMPIRE TECHNOLOGY DEVELOPMENT LLC2711 CENTERVILLE ROAD SUITE 400 WILMINGTON DE 19808

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kan, Edwin Ithaca, US 11 125
Ma, Yanjun Bellevue, US 113 2715

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