Multi-die interface for semiconductor testing and method of manufacturing same
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United States of America Patent
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Apr 3, 2018
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app pub date -
Nov 11, 2015
filing date -
Nov 11, 2015
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Abstract
The present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.
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