Semiconductor device with vertically integrated pHEMTs
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Aug 17, 2016
filing date -
Jul 8, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other.
First Claim
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International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
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