Structure and method for memory cell array
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Jun 16, 2017
filing date -
Jul 4, 2016
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Abstract
A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column.
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