Embedded SONOS based memory cells
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Mar 6, 2017
filing date -
Feb 26, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.
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Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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