Semiconductor package including substrates spaced by at least one electrical connecting element
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Aug 29, 2016
filing date -
Dec 19, 2014
priority date (Note) -
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Abstract
The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an upper surface, a semiconductor device mounted to the substrate, and a molding compound covering the lateral surface and the upper surface of the substrate and at least a portion of the semiconductor device. A surface of the semiconductor device is substantially coplanar with a surface of the molding compound.
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