Thermally enhanced semiconductor package with thermal additive and process for making the same
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United States of America Patent
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Feb 13, 2018
Grant Date -
Dec 14, 2017
app pub date -
Nov 16, 2016
filing date -
Jun 10, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
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