Computer implemented system and method for reducing failure in time soft errors of a circuit design
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 20, 2018
Issued Date -
N/A
app pub date -
Mar 23, 2016
filing date -
Mar 23, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully