Direct memory access controller
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Sep 21, 2015
filing date -
Dec 15, 2006
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Abstract
A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
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