Fully depleted region for reduced parasitic capacitance between a poly-silicon layer and a substrate region
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United States of America Patent
Stats
-
Mar 20, 2018
Issued Date -
N/A
app pub date -
Nov 16, 2015
filing date -
Nov 20, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.
First Claim
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International Classification(s)
- 2015 Application Filing Year
- B81C Class
- 517 Applications Filed
- 370 Patents Issued To-Date
- 71.57 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- B81C Class
- 11.11 % this patent is cited more than
- 7 Age
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