Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
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United States of America Patent
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Mar 13, 2018
Issued Date -
N/A
app pub date -
Nov 30, 2015
filing date -
Jun 5, 2012
priority date (Note) -
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Abstract
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
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