Accessing hidden diagnostic registers
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United States of America Patent
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Mar 13, 2018
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app pub date -
Jan 5, 2016
filing date -
Jan 5, 2016
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Abstract
A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.
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