Techniques and devices for performing arithmetic
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United States of America Patent
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Mar 13, 2018
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N/A
app pub date -
Oct 2, 2014
filing date -
Oct 2, 2013
priority date (Note) -
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Abstract
A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.
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