Techniques and devices for performing arithmetic

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United States of America Patent

PATENT NO 9916131
SERIAL NO

15025770

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Abstract

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A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

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Patent Owner(s)

Patent OwnerAddress
THE PENN STATE RESEARCH FOUNDATION304 OLD MAIN UNIVERSITY PARK PA 16802

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Walters,, III Eugene George Slippery Rock, US 1 19

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