Efficient loading and storing of data between memory and registers using a data structure for load and store addressing
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United States of America Patent
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Mar 13, 2018
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app pub date -
Sep 8, 2015
filing date -
Sep 8, 2014
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Abstract
Methods and apparatus for efficient loading of data from memory to registers and storing of data from registers to memory are described. In an embodiment, a processor comprises a data structure to which addresses which are used for load operations are pushed. Instead of independently generating addresses for a store operation, addresses are popped from the data structure and either used directly or an optional offset may first be applied to the popped address. In this way, a store operation and a load operation may be performed in parallel because they do not both require use of the logic which independently generates addresses for load/store operations. In various examples, the data structure is a FIFO structure.
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