Printing complex electronic circuits using a patterned hydrophobic layer
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United States of America Patent
Stats
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Mar 6, 2018
Issued Date -
N/A
app pub date -
Jan 13, 2017
filing date -
Mar 14, 2013
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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NTHDEGREE TECHNOLOGIES WORLDWIDE INC | 1320 W AUTO DRIVE TEMPE AS 85284-1025 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Blanchard, Richard Austin | Los Altos, US | 16 | 166 |
# of filed Patents : 16 Total Citations : 166 | |||
Lowenthal, Mark David | Vancouver, US | 76 | 1596 |
# of filed Patents : 76 Total Citations : 1596 | |||
Oraw, Bradley Steven | Chandler, US | 24 | 611 |
# of filed Patents : 24 Total Citations : 611 | |||
Ray, William Johnstone | Fountain Hills, US | 101 | 1553 |
# of filed Patents : 101 Total Citations : 1553 |
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Patent Citation Ranking
- 2 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Sep 6, 2025 |
11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 6, 2029 |
Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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Legal Events
Date | Code | Event | Description |
---|---|---|---|
Nov 08, 2010 | STCH | INFORMATION ON STATUS: PATENT DISCONTINUATION | free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
Oct 10, 2010 | FP | LAPSED DUE TO FAILURE TO PAY MAINTENANCE FEE | Effective Date: Oct 10, 2010 |
Oct 10, 2010 | LAPS | LAPSE FOR FAILURE TO PAY MAINTENANCE FEES | |
May 17, 2010 | REMI | MAINTENANCE FEE REMINDER MAILED | |
Oct 10, 2006 | I | Issuance | |
Aug 19, 2004 | P | Published | |
Jan 16, 2004 | F | Filing | |
Dec 25, 2003 | AS | ASSIGNMENT | free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOJIMA, TOMOYUKI;ABE, HIROAKI;MATSUKAWA, SHIGERU;AND OTHERS;REEL/FRAME:014896/0195 Owner name: TOKYO WELD CO., LTD., JAPAN Effective Date: Dec 25, 2003 |
Jan 20, 2003 | PD | Priority Date |

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