Semiconductor device chip selection
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United States of America Patent
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Mar 6, 2018
Issued Date -
N/A
app pub date -
Aug 24, 2015
filing date -
Jan 28, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
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