FPGA power management system
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United States of America Patent
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Mar 6, 2018
Issued Date -
N/A
app pub date -
Aug 27, 2014
filing date -
Sep 4, 2013
priority date (Note) -
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Abstract
An FPGA power management system includes a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus. The host power management integrated circuit includes a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device. The host power management integrated circuit further includes at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block. The host power management integrated circuit further includes a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail. The FPGA system power control block is configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit.
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