Biased impedance circuit, impedance adjustment circuit, and associated signal generator
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United States of America Patent
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Feb 27, 2018
Grant Date -
Nov 30, 2017
app pub date -
Apr 27, 2017
filing date -
May 27, 2016
priority date (Note) -
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Abstract
A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.
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