Interposer substrate designs for semiconductor packages
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United States of America Patent
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Feb 27, 2018
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app pub date -
Sep 27, 2013
filing date -
Sep 27, 2013
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Abstract
Semiconductor packages with multiple substrates can incorporate cavities in a portion of an upper substrate to minimize or reduce void formations during a molding process. The cavities can be formed substantially over the integrated circuit devices and not over the internal interconnects to further facilitate the flow of the molding compound. The combination with extension members or recesses on a top or exterior surface of the upper substrate can further cut down on bleeding or spill over of the molding compound between adjacent packages and improve device reliability and yield.
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