Wafer level fan-out package and method for manufacturing the same
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United States of America Patent
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Feb 27, 2018
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app pub date -
Feb 25, 2016
filing date -
Sep 24, 2015
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Abstract
A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.
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