Memory device with variable trim parameters

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United States of America Patent

PATENT NO 9905300
SERIAL NO

15417527

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Abstract

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A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.

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Patent Owner(s)

Patent OwnerAddress
SONY SEMICONDUCTOR SOLUTIONS CORPORATION4-14-1 ASAHICHO ATSUGI-SHI KANAGAWA 2430014

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kitagawa, Makoto Folsom, US 135 2222
Kunihiro, Takafumi Boise, US 22 261
Otsuka, Wataru Boise, US 28 474
Tsushima, Tomohito Boise, US 47 782

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