Asymmetrical emphasis in a memory data bus driver
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Feb 27, 2018
Grant Date -
Jul 27, 2017
app pub date -
Apr 6, 2017
filing date -
Dec 2, 2015
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.
First Claim
Other Claims data not available
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| Country | kind | publication No. | Filing Date |
|---|---|---|---|
| US | B1 | US9653147 | Dec 02, 2015 |
International Classification(s)
- 2017 Application Filing Year
- H04L Class
- 36365 Applications Filed
- 27259 Patents Issued To-Date
- 74.96 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H04L Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
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|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Aug 27, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Aug 27, 2029 |
