Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

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United States of America Patent

PATENT NO 9904756
SERIAL NO

14675516

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Abstract

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Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

International Classification(s)

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  • 2015 Application Filing Year
  • H01L Class
  • 25498 Applications Filed
  • 22451 Patents Issued To-Date
  • 88.06 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arkhipov, Alexandre San Jose, US 5 81
Powell, Giles V Alameda, US 14 135
Ruehl, Roland San Carlos, US 29 462
Sharma, Karun San Jose, US 22 185

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Patent Citation Ranking

  • 19 Citation Count
  • H01L Class
  • 87.83 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3689997611243481558461392216162801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500900095001000010500

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