Serial bus event notification in a memory device
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United States of America Patent
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Feb 27, 2018
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N/A
app pub date -
May 3, 2017
filing date -
May 15, 2014
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Abstract
A memory device incorporates a serial data bus coupled to a serial bus control circuit to provide access to error correction event notification information and error correction function configuration information. In some embodiments, the serial bus control circuit is in communication with a set of registers storing error correction event information and error correction function configuration information. The serial data bus enables access to the error correction control functions and to the error correction event notification information without interfering with and independent of the normal memory operation of the memory device.
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