Multi-stage delta-sigma pipelined successive approximation register analog-to-digital converter
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United States of America Patent
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Feb 20, 2018
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app pub date -
Jan 16, 2017
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Nov 28, 2016
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Abstract
A device includes a first conversion stage, a second conversion stage, and a first filter circuit. The first conversion stage is configured to perform a Delta-Sigma modulation based on an input signal, in order to generate a first quantized signal and a first residual signal. The second conversion stage is configured to perform a pipelined successive approximation algorithm in response to the first residual signal, in order to generate a second quantized signal. The first filter circuit is configured to perform a decimation process based on the first quantized signal and the second quantized signal to generate a digital output signal.
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