Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation compensation circuit, variation measurement method, and variation compensation method

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United States of America Patent

PATENT NO 9899993
SERIAL NO

14913309

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Abstract

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A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

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JAPAN SCIENCE AND TECHNOLOGY AGENCY4-1-8 HONCHO KAWAGUCHI-SHI SAITAMA 3320012 ?3320012

International Classification(s)

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  • 2014 Application Filing Year
  • H03K Class
  • 2384 Applications Filed
  • 2057 Patents Issued To-Date
  • 86.29 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances201420152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mahfuzul, Islam A K M Kyoto, JP 1 1
Onodera, Hidetoshi Kyoto, JP 4 23

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  • 1 Citation Count
  • H03K Class
  • 21.67 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges306935117261382111201 - 1011 - 2021 - 3031 - 4041 - 5051 - 6071 - 8081 - 9091 - 100100 +0501001502002503003504004505005506006507007508008509009501000

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