Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation compensation circuit, variation measurement method, and variation compensation method
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United States of America Patent
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Feb 20, 2018
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N/A
app pub date -
Jul 29, 2014
filing date -
Aug 19, 2013
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Abstract
A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.
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