Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses

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United States of America Patent

PATENT NO 9899476
SERIAL NO

14953692

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Abstract

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An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS INTERNATIONAL N V1228 PLAN-LES-OUATES GENEVA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bouton, Guilhem Peynier, FR 23 40
Fornara, Pascal Pourrieres, FR 115 341
Rivero, Christian Rousset, FR 83 289

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3689997611243481558461392216162801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500900095001000010500

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