Fan-out wafer level package structure
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United States of America Patent
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Feb 20, 2018
Grant Date -
Dec 28, 2017
app pub date -
Mar 27, 2017
filing date -
Jun 27, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.
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