Modeling memory in emulation based on cache
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United States of America Patent
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Feb 20, 2018
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app pub date -
Nov 13, 2015
filing date -
Nov 13, 2015
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Abstract
Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.
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