Scan chain circuit supporting logic self test pattern injection during run time
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United States of America Patent
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Feb 20, 2018
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app pub date -
Mar 16, 2016
filing date -
Mar 16, 2016
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Abstract
A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.
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