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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
DAEGU GYEONGBUK INSTITUTE OF SCIENCE AND TECHNOLOGY	333 TECHNO JUNGANG-DAERO HYEONPUNG-MYEON DALSEONG-GU DAEGU 42988

International Classification(s)

• A61B:DIAGNOSIS; SURGERY; IDENTIFICATION
• B25J:MANIPULATORS; CHAMBERS PROVIDED WITH MANIPULATION ....
• A61N:ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY;....

• 2014 Application Filing Year
• A61B Class
• 14296 Applications Filed
• 12053 Patents Issued To-Date
• 84.32 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Chang, Pyung Hun	Seoul, KR	11	55
# of filed Patents : 11 Total Citations : 55
Erkin, Gezgin	Izmir, TR	4	27
# of filed Patents : 4 Total Citations : 27

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Patent Citation Ranking

• 6 Citation Count
• A61B Class

• 20.51 % this patent is cited more than
• 7 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date
7.5 Year Payment	$3600.00	$1800.00	$900.00	Aug 20, 2025
11.5 Year Payment	$7400.00	$3700.00	$1850.00	Aug 20, 2029

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge - 7.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge - 11.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
February 20, 2018	US,9895559,B2   US9895559B2	GRANTED PATENT AS SECOND PUBLICATION
October 08, 2015	US,20150283407,A1   US20150283407A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 6781804

Protection of the logic well of a component including an integrated MOS power transistor

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Abstract

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The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

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Description

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Claims

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Claims data not available

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Legal Events

 

• FPAY2016
• AS2015
• FEPP2012
• FPAY2012
• FPAY2008
• I2005
• STCF2004
• FEPP2004
• P2004
• AS2003
• F2002
• PD2000

Date	Code	Event	Description
Jul 13, 2016	FPAY	FEE PAYMENT	year of fee payment: 12
Jul 09, 2015	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAG IAS GMBH;REEL/FRAME:036457/0415 Owner name: FFG WERKE GMBH, GERMANY Effective Date: Jul 09, 2015
Dec 01, 2012	FEPP	FEE PAYMENT PROCEDURE	free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY
Jul 12, 2012	FPAY	FEE PAYMENT	year of fee payment: 8
Jul 10, 2008	FPAY	FEE PAYMENT	year of fee payment: 4
Jan 18, 2005	I	Issuance
Dec 30, 2004	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Dec 03, 2004	FEPP	FEE PAYMENT PROCEDURE	free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY
Jan 08, 2004	P	Published
Jun 18, 2003	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIEGENER, WALTER;NAGELER, JURGEN;BAUER, WALTER;REEL/FRAME:014197/0863;SIGNING DATES FROM 20021115 TO 20021125 Owner name: WITZIG & FRANK GMBH, GERMANY
Dec 20, 2002	F	Filing
Jun 30, 2000	PD	Priority Date