Adjusting phase of a digital phase-locked loop
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United States of America Patent
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Feb 13, 2018
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N/A
app pub date -
Oct 3, 2016
filing date -
Oct 3, 2016
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Abstract
Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust output phase using a phase adjustment signal. In certain embodiments, the phase adjustment signal can be received in a signal path from an output of a time-to-digital converter of the DPLL to an input to the digitally controlled oscillator of the DPLL. Some embodiments relate to adjusting the output phase of the DPLL to reduce a relative phase difference between the output phase of the DPLL and an output phase of another DPLL.
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