Multi-level step-up converter topologies, control and soft start systems and methods
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United States of America Patent
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Feb 13, 2018
Issued Date -
N/A
app pub date -
May 12, 2017
filing date -
Mar 15, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pair.
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International Classification(s)
- 2017 Application Filing Year
- H02M Class
- 3298 Applications Filed
- 2665 Patents Issued To-Date
- 80.81 % Issued To-Date
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- 0 Citation Count
- H02M Class
- 0 % this patent is cited more than
- 7 Age
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