ESD protection circuit with false triggering prevention
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United States of America Patent
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Feb 13, 2018
Issued Date -
N/A
app pub date -
Dec 16, 2015
filing date -
Dec 16, 2015
priority date (Note) -
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Abstract
An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.
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