Data alignment implemented in a field programmable gate array (FPGA) device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 6, 2018
Issued Date -
N/A
app pub date -
Sep 8, 2016
filing date -
Sep 8, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully