Memory system and method for error correction of memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 6, 2018
Issued Date -
N/A
app pub date -
Mar 2, 2016
filing date -
Sep 30, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully