Self-aligned replacement metal gate spacerless vertical field effect transistor
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United States of America Patent
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Jan 30, 2018
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app pub date -
Feb 1, 2016
filing date -
Feb 1, 2016
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Abstract
A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
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