Methods of simultaneously forming bottom and top spacers on a vertical transistor device
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United States of America Patent
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Jan 30, 2018
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app pub date -
Sep 30, 2016
filing date -
Sep 30, 2016
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Abstract
One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure above a bottom source/drain (S/D) region and below a top source/drain (S/D) region, the gate structure comprising a gate electrode and a gate insulation layer, a first portion of the gate insulation layer being positioned between the gate electrode and the vertically oriented channel semiconductor structure, removing second portion and third portions of the gate insulation layer while leaving at least some of the first portion in position to define a top spacer recess and a lower spacer recess and performing a common deposition process to simultaneously form a top spacer in the top spacer recess and a lower spacer in the lower spacer recess.
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