Planar III-V field effect transistor (FET) on dielectric layer
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United States of America Patent
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Jan 30, 2018
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app pub date -
Feb 19, 2016
filing date -
Mar 12, 2014
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Abstract
A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
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