Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions
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United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Jul 2, 2014
filing date -
May 13, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
First Claim
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International Classification(s)
- 2014 Application Filing Year
- H01L Class
- 23828 Applications Filed
- 21803 Patents Issued To-Date
- 91.51 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
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