Array substrate and method for manufacturing the same, and display device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Sep 26, 2014
filing date -
Mar 17, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The invention provides a method for manufacturing an array substrate which comprises a gate driving circuit including a plurality of thin film transistors and connection gate lines each connected between gates of two adjacent thin film transistors, the method comprises steps of: step S1, forming a pattern including the gates of the thin film transistors and the connection gate lines on a base; step S2, forming a gate insulation layer above the pattern including the gates of the thin film transistors and the connection gate lines; step S3, forming a pattern including a gate line protecting layer on the gate insulation layer, wherein the gate line protecting layer is above the connection gate lines; and step S4, forming a pattern including the sources and drains of the thin film transistors. The invention also provides an array substrate which is manufactured by above method, and a display device comprising the same.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2014 Application Filing Year
- H01L Class
- 23828 Applications Filed
- 21803 Patents Issued To-Date
- 91.51 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 30, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 30, 2029 |
