Sequential write and sequential write verify in memory device
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Dec 23, 2014
filing date -
Dec 11, 2014
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Abstract
Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.
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