SRAM cell with dynamic split ground and split wordline
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United States of America Patent
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Jan 30, 2018
Issued Date -
N/A
app pub date -
Oct 6, 2016
filing date -
Dec 2, 2014
priority date (Note) -
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Abstract
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
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