Overvoltage protection for a fine grained negative wordline scheme
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United States of America Patent
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Jan 30, 2018
Issued Date -
N/A
app pub date -
Dec 8, 2015
filing date -
Aug 4, 2014
priority date (Note) -
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Abstract
A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.
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